Area and power-efficient reconfigurable digital down converter on FPGA

This paper presents a field-programmable gate array (FPGA)-based digital down converter (DDC) that can reduce the bandwidth from about 70 MHz to 182.292 kHz. The proposed DDC consists of polyphase COordinate Rotation DIgital Computer (CORDIC) processor and multirate filter. advantage CORDIC is process with high sample rate input data produces computational efficient noiseless baseband spectrum. pipeline filter works at clock speed. Moreover, generates fractional factor using cubic B-spline Farrow coded optimal hardware description language (HDL) tested on Kintex-7 Xilinx FPGA as target device. Experimental results indicate design saves chip area, power consumption operates speed without loss any functionality. Additionally, offers sufficient spurious-free dynamic range (SFDR) less than 1 Hz frequency resolution output.